sw8l(wkTechnexion Pico i.MX7D Board !technexion,imx7d-picofsl,imx7dchosenmemory,memoryaliases%8/soc/aips-bus@30000000/gpio@30200000%>/soc/aips-bus@30000000/gpio@30210000%D/soc/aips-bus@30000000/gpio@30220000%J/soc/aips-bus@30000000/gpio@30230000%P/soc/aips-bus@30000000/gpio@30240000%V/soc/aips-bus@30000000/gpio@30250000%\/soc/aips-bus@30000000/gpio@30260000$b/soc/aips-bus@30800000/i2c@30a20000$g/soc/aips-bus@30800000/i2c@30a30000$l/soc/aips-bus@30800000/i2c@30a40000$q/soc/aips-bus@30800000/i2c@30a50000&v/soc/aips-bus@30800000/usdhc@30b40000&{/soc/aips-bus@30800000/usdhc@30b50000&/soc/aips-bus@30800000/usdhc@30b600009/soc/aips-bus@30800000/spba-bus@30800000/serial@308600009/soc/aips-bus@30800000/spba-bus@30800000/serial@308900009/soc/aips-bus@30800000/spba-bus@30800000/serial@30880000'/soc/aips-bus@30800000/serial@30a60000'/soc/aips-bus@30800000/serial@30a70000'/soc/aips-bus@30800000/serial@30a80000'/soc/aips-bus@30800000/serial@30a900006/soc/aips-bus@30800000/spba-bus@30800000/spi@308200006/soc/aips-bus@30800000/spba-bus@30800000/spi@308300006/soc/aips-bus@30800000/spba-bus@30800000/spi@30840000$/soc/aips-bus@30400000/spi@30630000cpusidle-statespscicpu-sleep-wait!arm,idle-stated2'8cpu@0!arm,cortex-a7,cpu@D;]Tlbiy8cpu@1!arm,cortex-a7,cpu@D;]yi89clock-cki !fixed-clockDckil8clock-osc !fixed-clockDn6osc8usbphynop1!usb-nop-xceivb main_clk8%usbphynop3!usb-nop-xceivbn main_clk8(pmu!arm,cortex-a7-pmu \replicator!arm,coresight-replicatorout-portsport@0@endpoint8port@1@endpoint8in-portsportendpoint8tempmon!fsl,imx7d-tempmon 1  *calibtemp_gradebtimer!arm,armv7-timer 0   soc !simple-bus;funnel@30041000#!arm,coresight-funnelarm,primecell@0bJ apb_pclkin-portsportendpoint 8port@1@endpoint8:out-portsportendpoint8etm@3007c000"!arm,coresight-etm3xarm,primecell@0BbJ apb_pclkout-portsportendpoint8 funnel@30083000#!arm,coresight-funnelarm,primecell@00bJ apb_pclkin-portsport@0@endpoint8port@1@endpointout-portsportendpoint8etf@30084000 !arm,coresight-tmcarm,primecell@0@bJ apb_pclkin-portsportendpoint8out-portsportendpoint8etr@30086000 !arm,coresight-tmcarm,primecell@0`bJ apb_pclkin-portsportendpoint8tpiu@30087000!!arm,coresight-tpiuarm,primecell@0pbJ apb_pclkin-portsportendpoint8interrupt-controller@31001000!arm,cortex-a7-gic  FW  @11 1@ 1` 8 aips-bus@30000000!fsl,aips-bussimple-bus@0@;gpio@30200000!fsl,imx7d-gpiofsl,imx35-gpio@0 @Al|WF gpio@30210000!fsl,imx7d-gpiofsl,imx35-gpio@0!BCl|WF gpio@30220000!fsl,imx7d-gpiofsl,imx35-gpio@0"DEl|WF-gpio@30230000!fsl,imx7d-gpiofsl,imx35-gpio@0#FGl|WFJ8<gpio@30240000!fsl,imx7d-gpiofsl,imx35-gpio@0$HIl|WFbgpio@30250000!fsl,imx7d-gpiofsl,imx35-gpio@0%JKl|WFtgpio@30260000!fsl,imx7d-gpiofsl,imx35-gpio@0&LMl|WFwdog@30280000!fsl,imx7d-wdtfsl,imx21-wdt@0( NbBdefaultokaywdog@30290000!fsl,imx7d-wdtfsl,imx21-wdt@0) Ob disabledwdog@302a0000!fsl,imx7d-wdtfsl,imx21-wdt@0*  b disabledwdog@302b0000!fsl,imx7d-wdtfsl,imx21-wdt@0+ mb disablediomuxc-lpsr@302c0000!fsl,imx7d-iomuxc-lpsr@0,8wificlkgrp <}8+wdoggrp0t8gpt@302d0000!fsl,imx7d-gptfsl,imx6sx-gpt@0- 7b.ipgpergpt@302e0000!fsl,imx7d-gptfsl,imx6sx-gpt@0. 6b2ipgper disabledgpt@302f0000!fsl,imx7d-gptfsl,imx6sx-gpt@0/ 5b6ipgper disabledgpt@30300000!fsl,imx7d-gptfsl,imx6sx-gpt@00 4b:ipgper disabledkpp@30320000!fsl,imx7d-kppfsl,imx21-kpp@02 Pb disablediomuxc@30330000!fsl,imx7d-iomuxc@038i2c4grp0@@8#regap6212grphY8;usdhc2grp,Y(0Y4Y8Y<Y8*usdhc3grpDY@HYLYPYTYXY\Y`YdY8.usdhc3grp_100mhzDZ@HZLZPZTZXZ\Z`ZdZ8/usdhc3grp_200mhzD[@H[L[P[T[X[\[`[d[80enet1grpPh XDHLPT@,048<81i2c1grp0,@(@8 sai1grp``dh0\8uart5grp0dy`y8$usbotg_pwr<iomuxc-gpr@303400001!fsl,imx7d-iomuxc-gprfsl,imx6q-iomuxc-gprsyscon@04ocotp-ctrl@30350000!fsl,imx7d-ocotpsyscon@05bcalib@3c@<8 temp-grade@10@8 anatop@303600004!fsl,imx7d-anatopfsl,imx6q-anatopsysconsimple-bus@06138 regulator-vdd1p0d!fsl,anatop-regulatorvdd1p0d 5O0EZm 5O8regulator-vdd1p2!fsl,anatop-regulatorvdd1p2  0EZm snvs@30370000#!fsl,sec-v4.0-monsysconsimple-mfd@078snvs-rtc-lp!fsl,sec-v4.0-mon-rtc-lp)4b snvs-rtcsnvs-powerkey!fsl,sec-v4.0-pwrkey tccm@30380000!fsl,imx7d-ccm@08UVb ckiloscUW8src@30390000!fsl,imx7d-srcsyscon@09 Y87gpc@303a0000!fsl,imx7d-gpc@0:W WF 8pgcpgc-power-domain@1@%86aips-bus@30400000!fsl,aips-bussimple-bus@0@@;adc@30610000!fsl,imx7d-adc@0a bbadc disabledadc@30620000!fsl,imx7d-adc@0b cbadc disabledspi@30630000 !fsl,imx7d-ecspifsl,imx51-ecspi@0c "b  ipgper disabledpwm@30660000!fsl,imx7d-pwmfsl,imx27-pwm@0f Qbipgper2 disabledpwm@30670000!fsl,imx7d-pwmfsl,imx27-pwm@0g Rbipgper2 disabledpwm@30680000!fsl,imx7d-pwmfsl,imx27-pwm@0h Sbipgper2 disabledpwm@30690000!fsl,imx7d-pwmfsl,imx27-pwm@0i Tbipgper2 disabledlcdif@30730000 !fsl,imx7d-lcdiffsl,imx28-lcdif@0s b~~pixaxi disabledaips-bus@30800000!fsl,aips-bussimple-bus@0@;spba-bus@30800000!fsl,spba-bussimple-bus@0;spi@30820000 !fsl,imx7d-ecspifsl,imx51-ecspi@0 bipgper disabledspi@30830000 !fsl,imx7d-ecspifsl,imx51-ecspi@0  bipgper disabledspi@30840000 !fsl,imx7d-ecspifsl,imx51-ecspi@0 !bipgper disabledserial@30860000!fsl,imx7d-uartfsl,imx6q-uart@0 bipgper disabledserial@30890000!fsl,imx7d-uartfsl,imx6q-uart@0 bipgper disabledserial@30880000!fsl,imx7d-uartfsl,imx6q-uart@0 bipgper disabledsai@308a0000=!fsl,imx7d-saifsl,imx6sx-sai@0 _ bbusmclk1mclk2mclk3Nrxtx X okaydefaultw8>sai@308b0000=!fsl,imx7d-saifsl,imx6sx-sai@0 ` bbusmclk1mclk2mclk3Nrxtx X   disabledsai@308c0000=!fsl,imx7d-saifsl,imx6sx-sai@0 2 bbusmclk1mclk2mclk3Nrxtx X   disabledcaam@30900000 !fsl,sec-v4.0@0 ;0 [bZ ipgaclkjr0@1000!fsl,sec-v4.0-job-ring@ ijr1@2000!fsl,sec-v4.0-job-ring@  jjr1@3000!fsl,sec-v4.0-job-ring@0 rcan@30a00000$!fsl,imx7d-flexcanfsl,imx6q-flexcan@0 nbipgper disabledcan@30a10000$!fsl,imx7d-flexcanfsl,imx6q-flexcan@0 obipgper disabledi2c@30a20000!fsl,imx7d-i2cfsl,imx21-i2c@0 #bokayDdefault sgtl5000@a=@  !fsl,sgtl5000bJ]!i"8?i2c@30a30000!fsl,imx7d-i2cfsl,imx21-i2c@0 $b disabledi2c@30a40000!fsl,imx7d-i2cfsl,imx21-i2c@0 %b disabledi2c@30a50000!fsl,imx7d-i2cfsl,imx21-i2c@0 &bokaydefault#pfuze3000@8!fsl,pfuze3000@regulatorssw1a `2Zvjsw1b `vjsw2w@:vsw3 -PvswbstLK@N0vsnvsB@-vvrefddrvvldo1w@2Zvldo2 5vccsd+|2Zv33+|2Zvldo3w@2Zvldo4w@2Zserial@30a60000!fsl,imx7d-uartfsl,imx6q-uart@0 bipgper disabledserial@30a70000!fsl,imx7d-uartfsl,imx6q-uart@0 bipgperokaydefault$ serial@30a80000!fsl,imx7d-uartfsl,imx6q-uart@0 bipgper disabledserial@30a90000!fsl,imx7d-uartfsl,imx6q-uart@0 ~bipgper disabledmailbox@30aa0000!fsl,imx7s-mufsl,imx6sx-mu@0 Xb disabledmailbox@30ab0000!fsl,imx7s-mufsl,imx6sx-mu@0 ab disabledusb@30b10000!fsl,imx7d-usbfsl,imx27-usb@0 +b%&okay'usb@30b30000!fsl,imx7d-usbfsl,imx27-usb@0 (b()hsic host disabledusbmisc@30b10200$!fsl,imx7d-usbmiscfsl,imx6q-usbmisc@08&usbmisc@30b30200$!fsl,imx7d-usbmiscfsl,imx6q-usbmisc@08)usdhc@30b40000!!fsl,imx7d-usdhcfsl,imx6sl-usdhc@0 bV ipgahbper! disabledusdhc@30b50000!!fsl,imx7d-usdhcfsl,imx6sl-usdhc@0 bV ipgahbper!okaydefault*++4BX,d-usdhc@30b60000!!fsl,imx7d-usdhcfsl,imx6sl-usdhc@0 bV ipgahbper!okay"defaultstate_100mhzstate_200mhz.o/y0ׄ+4sdma@30bd0000!fsl,imx7d-sdmafsl,imx35-sdma@0 bZipgahbimx/sdma/sdma-imx7d.bin8ethernet@30be0000!fsl,imx7d-fecfsl,imx6sx-fec@0int0int1int2pps0xvwy(bR*"ipgahbptpenet_clk_refenet_outokaydefault1+rgmii2mdioethernet-phy@1!ethernet-phy-ieee802.3-c22@okay82usb@30b20000!fsl,imx7d-usbfsl,imx27-usb@0 *b34okay5 hostusbmisc@30b20200$!fsl,imx7d-usbmiscfsl,imx6q-usbmisc@084ethernet@30bf0000!fsl,imx7d-fecfsl,imx6sx-fec@0int0int1int2pps0fdeg(bR*"ipgahbptpenet_clk_refenet_out disabledpcie@33800000!fsl,imx7d-pciesnps,dw-pcie@3@O dbiconfig,pci0;O@@$ zmsiF.A } | { zbr+vpciepcie_buspcie_physw)+Ob6p777wpciephyappsturnoff disableddma-apbh@33000000&!fsl,imx7d-dma-apbhfsl,imx28-dma-apbh@3 0    gpmi0gpmi1gpmi2gpmi3b88gpmi-nand@33002000!fsl,imx7d-gpmi-nand@3 3@@gpmi-nandbch bchbgpmi_iogpmi_bch_apbX8Nrx-tx disabled(etm@3007d000"!arm,coresight-etm3xarm,primecell@0 VB9bJ apb_pclkout-portsportendpoint:8opp-table!operating-points-v28opp-792000000/4Iopp-996000000;]g8Iusbphynop2!usb-nop-xceivb main_clk83memory@80000000@regulator-ap6212!regulator-fixeddefault;AP62122Z2Z <8,regulator-2p5v!regulator-fixed2P5V&%&%8!regulator-3p3v!regulator-fixed3P3V2Z2Zregulator-usb-otg1-vbus!regulator-fixedusb_otg1_vbusLK@LK@ <8'regulator-usb-otg2-vbus!regulator-fixedusb_otg2_vbusLK@LK@85regulator-vref-1v8!regulator-fixed vref-1v8w@w@8"usdhc2_pwrseq!mmc-pwrseq-simplebW ext_clock8-sound!simple-audio-cardimx7-sgtl5000i2s,=N=simple-audio-card,cpum>simple-audio-card,codecm?bJ8= #address-cells#size-cellsmodelcompatibledevice_typegpio0gpio1gpio2gpio3gpio4gpio5gpio6i2c0i2c1i2c2i2c3mmc0mmc1mmc2serial0serial1serial2serial3serial4serial5serial6spi0spi1spi2spi3entry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usphandleregclock-frequencyclock-latencyclockscpu-idle-statesoperating-points-v2#cooling-cells#clock-cellsclock-output-namesclock-names#phy-cellsinterrupt-parentinterruptsinterrupt-affinityremote-endpointfsl,tempmonnvmem-cellsnvmem-cell-namesrangescpu#interrupt-cellsinterrupt-controllergpio-controller#gpio-cellsgpio-rangespinctrl-namespinctrl-0fsl,ext-reset-outputstatusfsl,input-selfsl,pinsregulator-nameregulator-min-microvoltregulator-max-microvoltanatop-reg-offsetanatop-vol-bit-shiftanatop-vol-bit-widthanatop-min-bit-valanatop-min-voltageanatop-max-voltageanatop-enable-bitregmaplinux,keycodewakeup-sourceassigned-clocksassigned-clock-parentsassigned-clock-rates#reset-cells#power-domain-cellspower-supply#pwm-cells#sound-dai-cellsdma-namesdmasVDDA-supplyVDDIO-supplyregulator-boot-onregulator-always-onregulator-ramp-delay#mbox-cellsfsl,mu-side-bfsl,usbphyfsl,usbmiscphy-clkgate-delay-usvbus-supplyphy_typedr_mode#index-cellsbus-widthno-1-8-vnon-removablekeep-power-in-suspendvmmc-supplymmc-pwrseqpinctrl-1pinctrl-2fsl,tuning-step#dma-cellsfsl,sdma-ram-script-nameinterrupt-namesfsl,num-tx-queuesfsl,num-rx-queuesphy-modephy-handlefsl,magic-packetreg-namesbus-rangenum-lanesinterrupt-map-maskinterrupt-mapfsl,max-link-speedpower-domainsresetsreset-namesdma-channelsarm,primecell-periphidopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendgpioenable-active-highsimple-audio-card,namesimple-audio-card,formatsimple-audio-card,bitclock-mastersimple-audio-card,frame-mastersound-dai