Ð þíWƒ8QÌ(·Q”,radxa,rockrockchip,rk3188 7Radxa Rockaliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/dwmmc@1021c000f/dwmmc@10214000l/dwmmc@10218000r/serial@10124000z/serial@10126000‚/serial@20064000Š/serial@20068000’/spi@20070000—/spi@20074000amba ,simple-busœdma-controller@20018000,arm,pl330arm,primecell£ €@§²½ØÀ ßapb_pclkë1dma-controller@2001c000,arm,pl330arm,primecell£ À@§²½ØÀ ßapb_pclk ódisableddma-controller@20078000,arm,pl330arm,primecell£ €@§²½ØÁ ßapb_pclkëoscillator ,fixed-clockún6 xin24mgpu@10090000",rockchip,rk3188-maliarm,mali-400£ ØÅÅ ßcorebus*Å:õáOxóokayx§ 5Vgpgpmmupp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3l2-cache-controller@10138000,arm,pl310-cache£€ftë,scu@1013c000,arm,cortex-a9-scu£Àglobal-timer@1013c200,arm,cortex-a9-global-timer£  § Ø ódisabledlocal-timer@1013c600,arm,cortex-a9-twd-timer£Æ  § Øinterrupt-controller@1013d000,arm,cortex-a9-gic€•£ÐÁëserial@10124000&,rockchip,rk3188-uartsnps,dw-apb-uart£@ §"¦°ßbaudclkapb_pclkØ@Lóokay½defaultËserial@10126000&,rockchip,rk3188-uartsnps,dw-apb-uart£` §#¦°ßbaudclkapb_pclkØAMóokay½defaultËusb@10180000,rockchip,rk3066-usbsnps,dwc2£ §ØÃßotgÕotgÝïþ€€@@   usb2-phyóokayusb@101c0000 ,snps,dwc2£ §ØÉßotgÕhost  usb2-phyóokayethernet@10204000,rockchip,rk3188-emac£ @< §ØÄD ßhclkmacref)d3rmiióokay½default Ë < @ ethernet-phy@0£ §ë dwmmc@10214000,rockchip,rk2928-dw-mshc£!@ §ØÀHßbiuciuKPrx-txZOQeresetóokay½defaultËq}‡™ªdwmmc@10218000,rockchip,rk2928-dw-mshc£!€ §ØÁIßbiuciuKPrx-txZORereset ódisableddwmmc@1021c000,rockchip,rk2928-dw-mshc£!À §ØÂJßbiuciuKPrx-txZOSereset ódisabledpmu@20004000&,rockchip,rk3066-pmusysconsimple-mfd£ @ë3reboot-mode,syscon-reboot-modeµ@¼RBÃÈRBÃÖRBà æRBÃgrf@20008000,syscon£ €ëi2c@2002d000,rockchip,rk3188-i2c£ Ð §(ßi2cØP ódisabled½defaultËi2c@2002f000,rockchip,rk3188-i2c£ ð §)ØQßi2cóokay½defaultËú€rtc@51,haoyu,hym8563£Q§ ½defaultË xin32kact8846@5a,active-semi,act8846£Zóokayò½defaultË  +6BNregulatorsREG1ZVCC_DDRiO€O€™REG2ZVDD_LOGiB@B@™REG3ZVDD_ARMi Yø™p™ë-REG4ZVCC_IOi2Z 2Z ™ëREG5ZVDD_10iB@B@™REG6 ZVDD_HDMIi&% &% ™REG7ZVCC_18iw@w@™REG8ZVCCA_33i2Z 2Z ™REG9 ZVCC_RMIIi2Z 2Z ë REG10 ZVCCIO_WLi2Z 2Z ™REG11 ZVCC18_IOiw@w@™REG12ZVCC_28i*¹€*¹€™pwm@20030000,rockchip,rk2928-pwm£ ­ØF ódisabled½defaultËpwm@20030010,rockchip,rk2928-pwm£ ­ØFóokay½defaultËwatchdog@2004c000 ,rockchip,rk3188-wdtsnps,dw-wdt£ ÀØK §3óokaypwm@20050020,rockchip,rk2928-pwm£  ­ØGóokay½defaultËpwm@20050030,rockchip,rk2928-pwm£ 0­ØGóokay½defaultËi2c@20056000,rockchip,rk3188-i2c£ ` §*ØRßi2c ódisabled½defaultËi2c@2005a000,rockchip,rk3188-i2c£   §+ØSßi2c ódisabled½defaultË i2c@2005e000,rockchip,rk3188-i2c£ à §4ØTßi2c ódisabled½defaultË!serial@20064000&,rockchip,rk3188-uartsnps,dw-apb-uart£ @ §$¦°ßbaudclkapb_pclkØBNóokay½defaultË"serial@20068000&,rockchip,rk3188-uartsnps,dw-apb-uart£ € §%¦°ßbaudclkapb_pclkØCOóokay½defaultË#saradc@2006c000,rockchip,saradc£ À §¸ØGJßsaradcapb_pclkOW esaradc-apb ódisabledspi@20070000(,rockchip,rk3188-spirockchip,rk3066-spiØEHßspiclkapb_pclk §&£ K  Ptxrx ódisabled½defaultË$%&'spi@20074000(,rockchip,rk3188-spirockchip,rk3066-spiØFIßspiclkapb_pclk §'£ @K  Ptxrx ódisabled½defaultË()*+cpusÊrockchip,rk3066-smpcpu@0Øcpu,arm,cortex-a9ä,£@õ‰@™p›@ÐO€Œ0a€g8 s€à˜ 'À~ð°ÀHÂÀ Yøœ@Ø-cpu@1Øcpu,arm,cortex-a9ä,£cpu@2Øcpu,arm,cortex-a9ä,£cpu@3Øcpu,arm,cortex-a9ä,£display-subsystem,rockchip,display-subsystem ./sram@10080000 ,mmio-sram£€ œ€smp-sram@0,rockchip,rk3066-smp-sram£Pvop@1010c000,rockchip,rk3188-vop£À § ØþÍßaclk_vopdclk_vophclk_vopOdef eaxiahbdclk ódisabledportë.vop@1010e000,rockchip,rk3188-vop£à §ØÄ¿Îßaclk_vopdclk_vophclk_vopOghi eaxiahbdclk ódisabledportë/timer@2000e000,,rockchip,rk3188-timerrockchip,rk3288-timer£ à  §.ØWE ßtimerpclktimer@200380a0,,rockchip,rk3188-timerrockchip,rk3288-timer£ €   §@ØZB ßtimerpclki2s@1011a000(,rockchip,rk3188-i2srockchip,rk3066-i2s£   § ½defaultË0K11Ptxrxßi2s_hclki2s_clkØÆK&A ódisabledsound@1011e000,,rockchip,rk3188-spdifrockchip,rk3066-spdif£à [ ßhclkmclkØÅNK1Ptx § ½defaultË2óokayë7clock-controller@20000000,rockchip,rk3188-cru£  lëefuse@20010000,rockchip,rk3188-efuse£ @Ø[ ßpclk_efusecpu_leakage@17£phy0,rockchip,rk3188-usb-phyrockchip,rk3288-usb-phyóokayusb-phy@10cy£ ØQßphyclk ëusb-phy@11cy£ØRßphyclk ëpinctrl,rockchip,rk3188-pinctrl„3œgpio0@2000a000,rockchip,rk3188-gpio-bank0£   §6ØU‘¡€•ëgpio1@2003c000,rockchip,gpio-bank£ À §7ØV‘¡€•gpio2@2003e000,rockchip,gpio-bank£ à §8ØW‘¡€•ë:gpio3@20080000,rockchip,gpio-bank£  §9ØX‘¡€•ë pcfg_pull_up­ë5pcfg_pull_downºpcfg_pull_noneÉë4emmcemmc-clkÖ4emmc-cmdÖ5emmc-rstÖ4emacemac-xfer€Ö44444444ëemac-mdio Ö44ë i2c0i2c0-xfer Ö44ëi2c1i2c1-xfer Ö44ëi2c2i2c2-xfer Ö44ëi2c3i2c3-xfer Ö44ë i2c4i2c4-xfer Ö44ë!lcdc1lcdc1-dclkÖ4lcdc1-denÖ4lcdc1-hsyncÖ4lcdc1-vsyncÖ4ldcd1-rgb24€Ö444444444 4 4 4 4 44444444444pwm0pwm0-outÖ4ëpwm1pwm1-outÖ4ëpwm2pwm2-outÖ4ëpwm3pwm3-outÖ4ëspi0spi0-clkÖ5ë$spi0-cs0Ö5ë'spi0-txÖ5ë%spi0-rxÖ5ë&spi0-cs1Ö5spi1spi1-clkÖ5ë(spi1-cs0Ö5ë+spi1-rxÖ5ë*spi1-txÖ5ë)spi1-cs1Ö5uart0uart0-xfer Ö54ëuart0-ctsÖ4uart0-rtsÖ4uart1uart1-xfer Ö54ëuart1-ctsÖ4uart1-rtsÖ4uart2uart2-xfer Ö5 4ë"uart3uart3-xfer Ö 5 4ë#uart3-ctsÖ 4uart3-rtsÖ 4sd0sd0-clkÖ4ësd0-cmdÖ4ësd0-cdÖ4ësd0-wpÖ 4sd0-pwrÖ4sd0-bus-width1Ö4sd0-bus-width4@Ö4444ësdmmc-pwrÖ4ë<sd1sd1-clkÖ4sd1-cmdÖ4sd1-cdÖ4sd1-wpÖ4sd1-bus-width1Ö4sd1-bus-width4@Ö4444i2s0i2s0-bus`Ö444444ë0spdifspdif-txÖ4ë2pcfg-output-lowäë6act8846act8846-dvs0-ctlÖ6ëhym8563rtc-intÖ5ëlan8720aphy-intÖ5ë ir-receiverir-recv-pinÖ 4ë9usbhost-vbus-drvÖ4ë=otg-vbus-drvÖ4ë;memory@60000000Ømemory£`€gpio-keys ,gpio-keysïpower út GPIO Key Power"0dgpio-leds ,gpio-ledsgreen rock:green:user1 ú Boffblue rock:blue:user2 úBoffsleep rock:red:power úBoffsound,simple-audio-cardPSPDIFsimple-audio-card,dai-link@1cpug7codecg8spdif-out,linux,spdif-dit[ë8gpio-ir-receiver,gpio-ir-receiver ú ½defaultË9usb-otg-regulator,regulator-fixedq „:½defaultË; Zotg-vbusiLK@LK@™‰sdmmc-regulator,regulator-fixed Zsdmmc-supplyi2Z 2Z  „ ½defaultË<›† ¬ëusb-host-regulator,regulator-fixedq „½defaultË= Zhost-pwriLK@LK@™‰vsys-regulator,regulator-fixedZvsysiLK@LK@‰ë #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4mshc0mshc1mshc2serial0serial1serial2serial3spi0spi1rangesreginterrupts#dma-cellsarm,pl330-broken-no-flushpclocksclock-namesphandlestatusclock-frequency#clock-cellsclock-output-namesassigned-clocksassigned-clock-ratesresetsinterrupt-namescache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthpinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modephyphy-supplydmasdma-namesfifo-depthreset-namesvmmc-supplybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpoffsetmode-normalmode-recoverymode-bootloadermode-loadersystem-power-controllervp1-supplyvp2-supplyvp3-supplyvp4-supplyinl1-supplyinl2-supplyinl3-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-on#pwm-cells#io-channel-cellsenable-methoddevice_typenext-level-cacheoperating-pointsclock-latencycpu0-supplyportsrockchip,playback-channelsrockchip,capture-channels#sound-dai-cells#reset-cells#phy-cellsrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disablerockchip,pinsoutput-lowautorepeatgpioslinux,codelabellinux,input-typewakeup-sourcedebounce-intervaldefault-statesimple-audio-card,namesound-daienable-active-highgpioregulator-boot-onstartup-delay-usvin-supply