cc1101.pdf page 54 

The CC1101 contains two 64 byte FIFOs, one for received data and one for data to be transmitted. 

CC1101́A64oCgFIFOiTXf[^RXf[^2ށj܂݂܂B 






The SPI interface is used to read from the RX FIFO and write to the TX FIFO. 

SPIC^[tF[X́ARX FIFO@TX FIFOւ̃ANZXɎgp܂B 






Section 10.5 contains details on the SPI FIFO access. 

10.5߂́ASPI FIFOANZXɊւڍׂ܂݂܂B 






The FIFO controller will detect overflow in the RX FIFO and underflow in the TX FIFO. 

FIFORg[́ATX FIFOARX FIFOŃA_[t[mł܂B









When writing to the TX FIFO it is the responsibility of the MCU to avoid TX FIFO overflow. 

TX FIFOɏƂATX FIFOI[o[t[邱ƂMCU̐ӔCłB 








A TX FIFO overflow will result in an error in the TX FIFO content. 

TX FIFOI[o[t[ɂȂƁATX FIFÕf[^e̓G[ƂȂ܂B 








Likewise, when reading the RX FIFO the MCU must avoid reading the RX FIFO past its empty value since a RX FIFO underflow will result in an error in the data read out of the RX FIFO. 




lɁB̂ƂAMCURX FIFOA_[t[ɂȂȂ΁ARX FIFO̓A_[t[ƂăG[̏ԂȂ̂ŁAłɋRXFIFOւ̃ANZXMCUŔȂ΂܂B




The chip status byte that is available on the SO pin while transferring the SPI header and contains the fill grade of the RX FIFO if the access is a read operation and the fill grade of the TX FIFO if the access is a write operation. 

SPIwb_ڂĂԁASOsŗp\ł`bvXe[^XoCgAāAANZXݑłȂ΃ANZXǍݑTX FIFÖtłȂ΁ARX FIFÖt܂݂܂B 







Section 10.1 on page 30 contains more details on this. 

30y[W̏̑10.1߂́AɊւ葽̏ڍׂ܂݂܂B 











The number of bytes in the RX FIFO and TX FIFO can be read from the status registers RXBYTES.NUM_RXBYTES and TXBYTES.NUM_TXBYTES respectively. 

RX FIFOTX FIFÕoCǵAꂼXe[^XWX^

RXBYTES.NUM_RXBYTES
TXBYTES.NUM_TXBYTES

烊[h邱Ƃł܂B



If a received data byte is written to the RX FIFO at the exact same time as the last byte in the RX FIFO is read over the SPI interface, the RX FIFO pointer is not properly updated and the last read byte will be duplicated. 

RX FIFO̍Ō̃oCgSPIC^[tF[Xɂēǂ܂1Mf[^oCgmȓRX FIFOɏȂ΁A
RX FIFO|C^[͂ƃAbvf[g܂AāAŌ̓ǂ܂ꂽoCg͕܂B 





To avoid this problem, the RX FIFO should never be emptied before the last byte of the packet is received. 

̖邽߂ɁA̍Ō̃oCg󂯎OɁARX FIFO͐΂ɏȂŉB





For packet lengths less than 64 bytes it is recommended to wait until the complete packet has been received before reading it out of the RX FIFO. 

̖邽߂ɁA̍Ō̃oCg󂯎OɁARX FIFO͌ċɂĂ͂܂B







For packet lengths less than 64 bytes it is recommended to wait until the complete packet has been received before reading it out of the RX FIFO. 


64oCg̔̃pPbg̏ꍇApPbgRXFIFOɎM܂ő҂ƂĂ܂B




If the packet length is larger than 64 bytes, the MCU must determine how many bytes can be read from the RX FIFO (RXBYTES.NUM_RXBYTES-1). 



64oCgȏ̃pPbg̏ꍇAMCU͉oCgRXFIFOǂݏoł邩肵Ȃ΂܂B



The following software routine can be used: 

ȉ̃\tgEFA[`gƂł܂B

















1 Read RXBYTES.NUM_RXBYTES repeatedly at a rate specified to be at least twice that of which RF bytes are received until the same value is returned twice; 

RXBYTES.NUM_RXBYTES̓ǂݍ݂JԂAȂƂxł邱ƂĂ闦ŁAǂRFoCgl܂Ŏ󂯎邩ƂꂪAԂ܂; 





store value in n. 


āAlnɕۊǂĂB 





2.If n # of bytes remaining in packet, read n-1 bytes from the RX FIFO. 


2.ApPbg̒#̃oCgcĂȂ΁A(n-1)oCgRXFIFOǂł B





3.Repeat steps 1 and 2 until n = # of bytes remaining in packet.


3.oCgn = #܂ł̎c̃pPbgoCgAXebv12JԂĂ  





4.Read the remaining bytes from the RX FIFO. 


4.RXc̃oCgRXFIFOǂłB








The 4-bit FIFOTHR.FIFO_THR setting is used to program threshold points in the FIFOs. 


FIFOTHR.FIFO_THR4rbg̐ݒŁAFIFORX,TX̃f[^ʂύX邱Ƃł܂B









Table 36 lists the 16 FIFO_THR settings and the corresponding thresholds for the RX and TX FIFOs. 


\36́ARXTX FIFÔ߂16FIFO_THRZbeBOƑΉ邵lXg܂B 









The threshold value is coded in opposite directions for the RX FIFO and TX FIFO. This gives equal margin to the overflow and underflow conditions when the threshold is reached. 



臒lRX FIFOTX FIFÔ߂ɔΕŃR[h܂BThis̓I[o[t[ɓ}[W^܂AāAA_[t[ɂB邩ɂĂ킩܂B








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