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#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
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EVEX_INSTRUCTIONS()::
# EMITTING AADD (AADD-128-1-32)
{
ICLASS:      AADD
CPL:         3
CATEGORY:    APX
EXTENSION:   APXEVEX
ISA_SET:     APX_F_RAO_INT
EXCEPTIONS:  APX-EVEX-RAO-INT
REAL_OPCODE: Y
ATTRIBUTES:  ATOMIC DISP8_NO_SCALE NOTSX REQUIRES_ALIGNMENT_4B 
PATTERN:     EVV 0xFC VNP MAP4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() ND=0 NF=0 W0 VL128 mode64 NOEVSR ZEROING=0 EVAPX()
OPERANDS:    MEM0:rw:d:i32 REG0=GPR32_R():r:d:i32
IFORM:       AADD_MEMi32_GPR32i32_APX
}


# EMITTING AADD (AADD-128-1-64)
{
ICLASS:      AADD
CPL:         3
CATEGORY:    APX
EXTENSION:   APXEVEX
ISA_SET:     APX_F_RAO_INT
EXCEPTIONS:  APX-EVEX-RAO-INT
REAL_OPCODE: Y
ATTRIBUTES:  ATOMIC DISP8_NO_SCALE NOTSX REQUIRES_ALIGNMENT_8B 
PATTERN:     EVV 0xFC VNP MAP4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() ND=0 NF=0 W1 VL128 mode64 NOEVSR ZEROING=0 EVAPX()
OPERANDS:    MEM0:rw:q:i64 REG0=GPR64_R():r:q:i64
IFORM:       AADD_MEMi64_GPR64i64_APX
}


# EMITTING AAND (AAND-128-1-32)
{
ICLASS:      AAND
CPL:         3
CATEGORY:    APX
EXTENSION:   APXEVEX
ISA_SET:     APX_F_RAO_INT
EXCEPTIONS:  APX-EVEX-RAO-INT
REAL_OPCODE: Y
ATTRIBUTES:  ATOMIC DISP8_NO_SCALE NOTSX REQUIRES_ALIGNMENT_4B 
PATTERN:     EVV 0xFC V66 MAP4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() ND=0 NF=0 W0 VL128 mode64 NOEVSR ZEROING=0 EVAPX()
OPERANDS:    MEM0:rw:d:i32 REG0=GPR32_R():r:d:i32
IFORM:       AAND_MEMi32_GPR32i32_APX
}


# EMITTING AAND (AAND-128-1-64)
{
ICLASS:      AAND
CPL:         3
CATEGORY:    APX
EXTENSION:   APXEVEX
ISA_SET:     APX_F_RAO_INT
EXCEPTIONS:  APX-EVEX-RAO-INT
REAL_OPCODE: Y
ATTRIBUTES:  ATOMIC DISP8_NO_SCALE NOTSX REQUIRES_ALIGNMENT_8B 
PATTERN:     EVV 0xFC V66 MAP4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() ND=0 NF=0 W1 VL128 mode64 NOEVSR ZEROING=0 EVAPX()
OPERANDS:    MEM0:rw:q:i64 REG0=GPR64_R():r:q:i64
IFORM:       AAND_MEMi64_GPR64i64_APX
}


# EMITTING AOR (AOR-128-1-32)
{
ICLASS:      AOR
CPL:         3
CATEGORY:    APX
EXTENSION:   APXEVEX
ISA_SET:     APX_F_RAO_INT
EXCEPTIONS:  APX-EVEX-RAO-INT
REAL_OPCODE: Y
ATTRIBUTES:  ATOMIC DISP8_NO_SCALE NOTSX REQUIRES_ALIGNMENT_4B 
PATTERN:     EVV 0xFC VF2 MAP4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() ND=0 NF=0 W0 VL128 mode64 NOEVSR ZEROING=0 EVAPX()
OPERANDS:    MEM0:rw:d:i32 REG0=GPR32_R():r:d:i32
IFORM:       AOR_MEMi32_GPR32i32_APX
}


# EMITTING AOR (AOR-128-1-64)
{
ICLASS:      AOR
CPL:         3
CATEGORY:    APX
EXTENSION:   APXEVEX
ISA_SET:     APX_F_RAO_INT
EXCEPTIONS:  APX-EVEX-RAO-INT
REAL_OPCODE: Y
ATTRIBUTES:  ATOMIC DISP8_NO_SCALE NOTSX REQUIRES_ALIGNMENT_8B 
PATTERN:     EVV 0xFC VF2 MAP4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() ND=0 NF=0 W1 VL128 mode64 NOEVSR ZEROING=0 EVAPX()
OPERANDS:    MEM0:rw:q:i64 REG0=GPR64_R():r:q:i64
IFORM:       AOR_MEMi64_GPR64i64_APX
}


# EMITTING AXOR (AXOR-128-1-32)
{
ICLASS:      AXOR
CPL:         3
CATEGORY:    APX
EXTENSION:   APXEVEX
ISA_SET:     APX_F_RAO_INT
EXCEPTIONS:  APX-EVEX-RAO-INT
REAL_OPCODE: Y
ATTRIBUTES:  ATOMIC DISP8_NO_SCALE NOTSX REQUIRES_ALIGNMENT_4B 
PATTERN:     EVV 0xFC VF3 MAP4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() ND=0 NF=0 W0 VL128 mode64 NOEVSR ZEROING=0 EVAPX()
OPERANDS:    MEM0:rw:d:i32 REG0=GPR32_R():r:d:i32
IFORM:       AXOR_MEMi32_GPR32i32_APX
}


# EMITTING AXOR (AXOR-128-1-64)
{
ICLASS:      AXOR
CPL:         3
CATEGORY:    APX
EXTENSION:   APXEVEX
ISA_SET:     APX_F_RAO_INT
EXCEPTIONS:  APX-EVEX-RAO-INT
REAL_OPCODE: Y
ATTRIBUTES:  ATOMIC DISP8_NO_SCALE NOTSX REQUIRES_ALIGNMENT_8B 
PATTERN:     EVV 0xFC VF3 MAP4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() ND=0 NF=0 W1 VL128 mode64 NOEVSR ZEROING=0 EVAPX()
OPERANDS:    MEM0:rw:q:i64 REG0=GPR64_R():r:q:i64
IFORM:       AXOR_MEMi64_GPR64i64_APX
}


