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EVEX_INSTRUCTIONS()::
# EMITTING VADDPD (VADDPD-256-2)
{
ICLASS:      VADDPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():w:qq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
IFORM:       VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC
}


# EMITTING VADDPH (VADDPH-256-2)
{
ICLASS:      VADDPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():w:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC
}


# EMITTING VADDPS (VADDPS-256-2)
{
ICLASS:      VADDPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC
}


# EMITTING VCMPPD (VCMPPD-256-2)
{
ICLASS:      VCMPPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() SAE256() ZEROING=0 UIMM8()
OPERANDS:    REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b
IFORM:       VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_VL256RC
}


# EMITTING VCMPPH (VCMPPH-256-2)
{
ICLASS:      VCMPPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() ZEROING=0 UIMM8()
OPERANDS:    REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 IMM0:r:b
IFORM:       VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512_VL256RC
}


# EMITTING VCMPPS (VCMPPS-256-2)
{
ICLASS:      VCMPPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() ZEROING=0 UIMM8()
OPERANDS:    REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b
IFORM:       VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_VL256RC
}


# EMITTING VCVTDQ2PD (VCVTDQ2PD-256-2)
{
ICLASS:      VCVTDQ2PD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32
IFORM:       VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512_VL256RC
}


# EMITTING VCVTDQ2PH (VCVTDQ2PH-256-2)
{
ICLASS:      VCVTDQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32
IFORM:       VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512_VL256RC
}


# EMITTING VCVTDQ2PS (VCVTDQ2PS-256-2)
{
ICLASS:      VCVTDQ2PS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32
IFORM:       VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512_VL256RC
}


# EMITTING VCVTPD2DQ (VCVTPD2DQ-256-2)
{
ICLASS:      VCVTPD2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:i32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
IFORM:       VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256RC_VL256
}


# EMITTING VCVTPD2PH (VCVTPD2PH-256-2)
{
ICLASS:      VCVTPD2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
IFORM:       VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512_VL256RC
}


# EMITTING VCVTPD2PS (VCVTPD2PS-256-2)
{
ICLASS:      VCVTPD2PS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
IFORM:       VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256RC_VL256
}


# EMITTING VCVTPD2QQ (VCVTPD2QQ-256-2)
{
ICLASS:      VCVTPD2QQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
IFORM:       VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_VL256RC
}


# EMITTING VCVTPD2UDQ (VCVTPD2UDQ-256-2)
{
ICLASS:      VCVTPD2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:u32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
IFORM:       VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256RC_VL256
}


# EMITTING VCVTPD2UQQ (VCVTPD2UQQ-256-2)
{
ICLASS:      VCVTPD2UQQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
IFORM:       VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_VL256RC
}


# EMITTING VCVTPH2DQ (VCVTPH2DQ-256-2)
{
ICLASS:      VCVTPH2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_VL256RC
}


# EMITTING VCVTPH2PD (VCVTPH2PD-256-2)
{
ICLASS:      VCVTPH2PD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_FTZ 
PATTERN:     EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512_VL256RC
}


# EMITTING VCVTPH2PS (VCVTPH2PS-256-2)
{
ICLASS:      VCVTPH2PS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E11
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_FTZ 
PATTERN:     EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512_VL256RC
}


# EMITTING VCVTPH2PSX (VCVTPH2PSX-256-2)
{
ICLASS:      VCVTPH2PSX
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_FTZ 
PATTERN:     EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512_VL256RC
}


# EMITTING VCVTPH2QQ (VCVTPH2QQ-256-2)
{
ICLASS:      VCVTPH2QQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_VL256RC
}


# EMITTING VCVTPH2UDQ (VCVTPH2UDQ-256-2)
{
ICLASS:      VCVTPH2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_VL256RC
}


# EMITTING VCVTPH2UQQ (VCVTPH2UQQ-256-2)
{
ICLASS:      VCVTPH2UQQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_VL256RC
}


# EMITTING VCVTPH2UW (VCVTPH2UW-256-2)
{
ICLASS:      VCVTPH2UW
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_VL256RC
}


# EMITTING VCVTPH2W (VCVTPH2W-256-2)
{
ICLASS:      VCVTPH2W
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_VL256RC
}


# EMITTING VCVTPS2DQ (VCVTPS2DQ-256-2)
{
ICLASS:      VCVTPS2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_VL256RC
}


# EMITTING VCVTPS2PD (VCVTPS2PD-256-2)
{
ICLASS:      VCVTPS2PD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
IFORM:       VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512_VL256RC
}


# EMITTING VCVTPS2PH (VCVTPS2PH-256-2)
{
ICLASS:      VCVTPS2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E11
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR UIMM8()
OPERANDS:    REG0=XMM_B3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 IMM0:r:b
IFORM:       VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512_VL256RC
}


# EMITTING VCVTPS2PHX (VCVTPS2PHX-256-2)
{
ICLASS:      VCVTPS2PHX
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512_VL256RC
}


# EMITTING VCVTPS2QQ (VCVTPS2QQ-256-2)
{
ICLASS:      VCVTPS2QQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
IFORM:       VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_VL256RC
}


# EMITTING VCVTPS2UDQ (VCVTPS2UDQ-256-2)
{
ICLASS:      VCVTPS2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_VL256RC
}


# EMITTING VCVTPS2UQQ (VCVTPS2UQQ-256-2)
{
ICLASS:      VCVTPS2UQQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
IFORM:       VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_VL256RC
}


# EMITTING VCVTQQ2PD (VCVTQQ2PD-256-2)
{
ICLASS:      VCVTQQ2PD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i64
IFORM:       VCVTQQ2PD_YMMf64_MASKmskw_YMMi64_AVX512_VL256RC
}


# EMITTING VCVTQQ2PH (VCVTQQ2PH-256-2)
{
ICLASS:      VCVTQQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
IFORM:       VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_VL256RC
}


# EMITTING VCVTQQ2PS (VCVTQQ2PS-256-2)
{
ICLASS:      VCVTQQ2PS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
IFORM:       VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256RC_VL256
}


# EMITTING VCVTTPD2DQ (VCVTTPD2DQ-256-2)
{
ICLASS:      VCVTTPD2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:i32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
IFORM:       VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256RC_VL256
}


# EMITTING VCVTTPD2QQ (VCVTTPD2QQ-256-2)
{
ICLASS:      VCVTTPD2QQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
IFORM:       VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_VL256RC
}


# EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-256-2)
{
ICLASS:      VCVTTPD2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:u32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
IFORM:       VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256RC_VL256
}


# EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-256-2)
{
ICLASS:      VCVTTPD2UQQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
IFORM:       VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_VL256RC
}


# EMITTING VCVTTPH2DQ (VCVTTPH2DQ-256-2)
{
ICLASS:      VCVTTPH2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_VL256RC
}


# EMITTING VCVTTPH2QQ (VCVTTPH2QQ-256-2)
{
ICLASS:      VCVTTPH2QQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_VL256RC
}


# EMITTING VCVTTPH2UDQ (VCVTTPH2UDQ-256-2)
{
ICLASS:      VCVTTPH2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_VL256RC
}


# EMITTING VCVTTPH2UQQ (VCVTTPH2UQQ-256-2)
{
ICLASS:      VCVTTPH2UQQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_VL256RC
}


# EMITTING VCVTTPH2UW (VCVTTPH2UW-256-2)
{
ICLASS:      VCVTTPH2UW
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_VL256RC
}


# EMITTING VCVTTPH2W (VCVTTPH2W-256-2)
{
ICLASS:      VCVTTPH2W
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_VL256RC
}


# EMITTING VCVTTPS2DQ (VCVTTPS2DQ-256-2)
{
ICLASS:      VCVTTPS2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_VL256RC
}


# EMITTING VCVTTPS2QQ (VCVTTPS2QQ-256-2)
{
ICLASS:      VCVTTPS2QQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
IFORM:       VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_VL256RC
}


# EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-256-2)
{
ICLASS:      VCVTTPS2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_VL256RC
}


# EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-256-2)
{
ICLASS:      VCVTTPS2UQQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
IFORM:       VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_VL256RC
}


# EMITTING VCVTUDQ2PD (VCVTUDQ2PD-256-2)
{
ICLASS:      VCVTUDQ2PD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32
IFORM:       VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512_VL256RC
}


# EMITTING VCVTUDQ2PH (VCVTUDQ2PH-256-2)
{
ICLASS:      VCVTUDQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
IFORM:       VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512_VL256RC
}


# EMITTING VCVTUDQ2PS (VCVTUDQ2PS-256-2)
{
ICLASS:      VCVTUDQ2PS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
IFORM:       VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512_VL256RC
}


# EMITTING VCVTUQQ2PD (VCVTUQQ2PD-256-2)
{
ICLASS:      VCVTUQQ2PD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
IFORM:       VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512_VL256RC
}


# EMITTING VCVTUQQ2PH (VCVTUQQ2PH-256-2)
{
ICLASS:      VCVTUQQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
IFORM:       VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_VL256RC
}


# EMITTING VCVTUQQ2PS (VCVTUQQ2PS-256-2)
{
ICLASS:      VCVTUQQ2PS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
IFORM:       VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256RC_VL256
}


# EMITTING VCVTUW2PH (VCVTUW2PH-256-2)
{
ICLASS:      VCVTUW2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16
IFORM:       VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512_VL256RC
}


# EMITTING VCVTW2PH (VCVTW2PH-256-2)
{
ICLASS:      VCVTW2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16
IFORM:       VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512_VL256RC
}


# EMITTING VDIVPD (VDIVPD-256-2)
{
ICLASS:      VDIVPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():w:qq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
IFORM:       VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC
}


# EMITTING VDIVPH (VDIVPH-256-2)
{
ICLASS:      VDIVPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():w:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC
}


# EMITTING VDIVPS (VDIVPS-256-2)
{
ICLASS:      VDIVPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC
}


# EMITTING VFCMADDCPH (VFCMADDCPH-256-2)
{
ICLASS:      VFCMADDCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH 
PATTERN:     EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 REG3=YMM_B3():r:qq:2f16
IFORM:       VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_VL256RC
}


# EMITTING VFCMULCPH (VFCMULCPH-256-2)
{
ICLASS:      VFCMULCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH 
PATTERN:     EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():w:qq:2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 REG3=YMM_B3():r:qq:2f16
IFORM:       VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_VL256RC
}


# EMITTING VFIXUPIMMPD (VFIXUPIMMPD-256-2)
{
ICLASS:      VFIXUPIMMPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() SAE256() UIMM8()
OPERANDS:    REG0=YMM_R3():rw:qq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b
IFORM:       VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_VL256RC
}


# EMITTING VFIXUPIMMPS (VFIXUPIMMPS-256-2)
{
ICLASS:      VFIXUPIMMPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() UIMM8()
OPERANDS:    REG0=YMM_R3():rw:qq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b
IFORM:       VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_VL256RC
}


# EMITTING VFMADD132PD (VFMADD132PD-256-2)
{
ICLASS:      VFMADD132PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
IFORM:       VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC
}


# EMITTING VFMADD132PH (VFMADD132PH-256-2)
{
ICLASS:      VFMADD132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC
}


# EMITTING VFMADD132PS (VFMADD132PS-256-2)
{
ICLASS:      VFMADD132PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC
}


# EMITTING VFMADD213PD (VFMADD213PD-256-2)
{
ICLASS:      VFMADD213PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
IFORM:       VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC
}


# EMITTING VFMADD213PH (VFMADD213PH-256-2)
{
ICLASS:      VFMADD213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC
}


# EMITTING VFMADD213PS (VFMADD213PS-256-2)
{
ICLASS:      VFMADD213PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC
}


# EMITTING VFMADD231PD (VFMADD231PD-256-2)
{
ICLASS:      VFMADD231PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
IFORM:       VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC
}


# EMITTING VFMADD231PH (VFMADD231PH-256-2)
{
ICLASS:      VFMADD231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC
}


# EMITTING VFMADD231PS (VFMADD231PS-256-2)
{
ICLASS:      VFMADD231PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC
}


# EMITTING VFMADDCPH (VFMADDCPH-256-2)
{
ICLASS:      VFMADDCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH 
PATTERN:     EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 REG3=YMM_B3():r:qq:2f16
IFORM:       VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_VL256RC
}


# EMITTING VFMADDSUB132PD (VFMADDSUB132PD-256-2)
{
ICLASS:      VFMADDSUB132PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
IFORM:       VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC
}


# EMITTING VFMADDSUB132PH (VFMADDSUB132PH-256-2)
{
ICLASS:      VFMADDSUB132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC
}


# EMITTING VFMADDSUB132PS (VFMADDSUB132PS-256-2)
{
ICLASS:      VFMADDSUB132PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC
}


# EMITTING VFMADDSUB213PD (VFMADDSUB213PD-256-2)
{
ICLASS:      VFMADDSUB213PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
IFORM:       VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC
}


# EMITTING VFMADDSUB213PH (VFMADDSUB213PH-256-2)
{
ICLASS:      VFMADDSUB213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC
}


# EMITTING VFMADDSUB213PS (VFMADDSUB213PS-256-2)
{
ICLASS:      VFMADDSUB213PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC
}


# EMITTING VFMADDSUB231PD (VFMADDSUB231PD-256-2)
{
ICLASS:      VFMADDSUB231PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
IFORM:       VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC
}


# EMITTING VFMADDSUB231PH (VFMADDSUB231PH-256-2)
{
ICLASS:      VFMADDSUB231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC
}


# EMITTING VFMADDSUB231PS (VFMADDSUB231PS-256-2)
{
ICLASS:      VFMADDSUB231PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC
}


# EMITTING VFMSUB132PD (VFMSUB132PD-256-2)
{
ICLASS:      VFMSUB132PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
IFORM:       VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC
}


# EMITTING VFMSUB132PH (VFMSUB132PH-256-2)
{
ICLASS:      VFMSUB132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC
}


# EMITTING VFMSUB132PS (VFMSUB132PS-256-2)
{
ICLASS:      VFMSUB132PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC
}


# EMITTING VFMSUB213PD (VFMSUB213PD-256-2)
{
ICLASS:      VFMSUB213PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
IFORM:       VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC
}


# EMITTING VFMSUB213PH (VFMSUB213PH-256-2)
{
ICLASS:      VFMSUB213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC
}


# EMITTING VFMSUB213PS (VFMSUB213PS-256-2)
{
ICLASS:      VFMSUB213PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC
}


# EMITTING VFMSUB231PD (VFMSUB231PD-256-2)
{
ICLASS:      VFMSUB231PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
IFORM:       VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC
}


# EMITTING VFMSUB231PH (VFMSUB231PH-256-2)
{
ICLASS:      VFMSUB231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC
}


# EMITTING VFMSUB231PS (VFMSUB231PS-256-2)
{
ICLASS:      VFMSUB231PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC
}


# EMITTING VFMSUBADD132PD (VFMSUBADD132PD-256-2)
{
ICLASS:      VFMSUBADD132PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
IFORM:       VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC
}


# EMITTING VFMSUBADD132PH (VFMSUBADD132PH-256-2)
{
ICLASS:      VFMSUBADD132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC
}


# EMITTING VFMSUBADD132PS (VFMSUBADD132PS-256-2)
{
ICLASS:      VFMSUBADD132PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC
}


# EMITTING VFMSUBADD213PD (VFMSUBADD213PD-256-2)
{
ICLASS:      VFMSUBADD213PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
IFORM:       VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC
}


# EMITTING VFMSUBADD213PH (VFMSUBADD213PH-256-2)
{
ICLASS:      VFMSUBADD213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC
}


# EMITTING VFMSUBADD213PS (VFMSUBADD213PS-256-2)
{
ICLASS:      VFMSUBADD213PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC
}


# EMITTING VFMSUBADD231PD (VFMSUBADD231PD-256-2)
{
ICLASS:      VFMSUBADD231PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
IFORM:       VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC
}


# EMITTING VFMSUBADD231PH (VFMSUBADD231PH-256-2)
{
ICLASS:      VFMSUBADD231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC
}


# EMITTING VFMSUBADD231PS (VFMSUBADD231PS-256-2)
{
ICLASS:      VFMSUBADD231PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC
}


# EMITTING VFMULCPH (VFMULCPH-256-2)
{
ICLASS:      VFMULCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH 
PATTERN:     EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():w:qq:2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 REG3=YMM_B3():r:qq:2f16
IFORM:       VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_VL256RC
}


# EMITTING VFNMADD132PD (VFNMADD132PD-256-2)
{
ICLASS:      VFNMADD132PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
IFORM:       VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC
}


# EMITTING VFNMADD132PH (VFNMADD132PH-256-2)
{
ICLASS:      VFNMADD132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC
}


# EMITTING VFNMADD132PS (VFNMADD132PS-256-2)
{
ICLASS:      VFNMADD132PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC
}


# EMITTING VFNMADD213PD (VFNMADD213PD-256-2)
{
ICLASS:      VFNMADD213PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
IFORM:       VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC
}


# EMITTING VFNMADD213PH (VFNMADD213PH-256-2)
{
ICLASS:      VFNMADD213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC
}


# EMITTING VFNMADD213PS (VFNMADD213PS-256-2)
{
ICLASS:      VFNMADD213PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC
}


# EMITTING VFNMADD231PD (VFNMADD231PD-256-2)
{
ICLASS:      VFNMADD231PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
IFORM:       VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC
}


# EMITTING VFNMADD231PH (VFNMADD231PH-256-2)
{
ICLASS:      VFNMADD231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC
}


# EMITTING VFNMADD231PS (VFNMADD231PS-256-2)
{
ICLASS:      VFNMADD231PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC
}


# EMITTING VFNMSUB132PD (VFNMSUB132PD-256-2)
{
ICLASS:      VFNMSUB132PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
IFORM:       VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC
}


# EMITTING VFNMSUB132PH (VFNMSUB132PH-256-2)
{
ICLASS:      VFNMSUB132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC
}


# EMITTING VFNMSUB132PS (VFNMSUB132PS-256-2)
{
ICLASS:      VFNMSUB132PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC
}


# EMITTING VFNMSUB213PD (VFNMSUB213PD-256-2)
{
ICLASS:      VFNMSUB213PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
IFORM:       VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC
}


# EMITTING VFNMSUB213PH (VFNMSUB213PH-256-2)
{
ICLASS:      VFNMSUB213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC
}


# EMITTING VFNMSUB213PS (VFNMSUB213PS-256-2)
{
ICLASS:      VFNMSUB213PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC
}


# EMITTING VFNMSUB231PD (VFNMSUB231PD-256-2)
{
ICLASS:      VFNMSUB231PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
IFORM:       VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC
}


# EMITTING VFNMSUB231PH (VFNMSUB231PH-256-2)
{
ICLASS:      VFNMSUB231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC
}


# EMITTING VFNMSUB231PS (VFNMSUB231PS-256-2)
{
ICLASS:      VFNMSUB231PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():rw:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC
}


# EMITTING VGETEXPPD (VGETEXPPD-256-2)
{
ICLASS:      VGETEXPPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
IFORM:       VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512_VL256RC
}


# EMITTING VGETEXPPH (VGETEXPPH-256-2)
{
ICLASS:      VGETEXPPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512_VL256RC
}


# EMITTING VGETEXPPS (VGETEXPPS-256-2)
{
ICLASS:      VGETEXPPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512_VL256RC
}


# EMITTING VGETMANTPD (VGETMANTPD-256-2)
{
ICLASS:      VGETMANTPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() SAE256() NOEVSR UIMM8()
OPERANDS:    REG0=YMM_R3():w:qq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b
IFORM:       VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_VL256RC
}


# EMITTING VGETMANTPH (VGETMANTPH-256-2)
{
ICLASS:      VGETMANTPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR UIMM8()
OPERANDS:    REG0=YMM_R3():w:qq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 IMM0:r:b
IFORM:       VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_VL256RC
}


# EMITTING VGETMANTPS (VGETMANTPS-256-2)
{
ICLASS:      VGETMANTPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR UIMM8()
OPERANDS:    REG0=YMM_R3():w:qq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b
IFORM:       VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_VL256RC
}


# EMITTING VMAXPD (VMAXPD-256-2)
{
ICLASS:      VMAXPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() SAE256()
OPERANDS:    REG0=YMM_R3():w:qq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
IFORM:       VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC
}


# EMITTING VMAXPH (VMAXPH-256-2)
{
ICLASS:      VMAXPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256()
OPERANDS:    REG0=YMM_R3():w:qq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC
}


# EMITTING VMAXPS (VMAXPS-256-2)
{
ICLASS:      VMAXPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256()
OPERANDS:    REG0=YMM_R3():w:qq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC
}


# EMITTING VMINPD (VMINPD-256-2)
{
ICLASS:      VMINPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() SAE256()
OPERANDS:    REG0=YMM_R3():w:qq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
IFORM:       VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC
}


# EMITTING VMINPH (VMINPH-256-2)
{
ICLASS:      VMINPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256()
OPERANDS:    REG0=YMM_R3():w:qq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC
}


# EMITTING VMINPS (VMINPS-256-2)
{
ICLASS:      VMINPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256()
OPERANDS:    REG0=YMM_R3():w:qq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC
}


# EMITTING VMULPD (VMULPD-256-2)
{
ICLASS:      VMULPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():w:qq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
IFORM:       VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC
}


# EMITTING VMULPH (VMULPH-256-2)
{
ICLASS:      VMULPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():w:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC
}


# EMITTING VMULPS (VMULPS-256-2)
{
ICLASS:      VMULPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC
}


# EMITTING VRANGEPD (VRANGEPD-256-2)
{
ICLASS:      VRANGEPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() SAE256() UIMM8()
OPERANDS:    REG0=YMM_R3():w:qq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b
IFORM:       VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_VL256RC
}


# EMITTING VRANGEPS (VRANGEPS-256-2)
{
ICLASS:      VRANGEPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() UIMM8()
OPERANDS:    REG0=YMM_R3():w:qq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b
IFORM:       VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_VL256RC
}


# EMITTING VREDUCEPD (VREDUCEPD-256-2)
{
ICLASS:      VREDUCEPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() SAE256() NOEVSR UIMM8()
OPERANDS:    REG0=YMM_R3():w:qq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b
IFORM:       VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_VL256RC
}


# EMITTING VREDUCEPH (VREDUCEPH-256-2)
{
ICLASS:      VREDUCEPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR UIMM8()
OPERANDS:    REG0=YMM_R3():w:qq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 IMM0:r:b
IFORM:       VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_VL256RC
}


# EMITTING VREDUCEPS (VREDUCEPS-256-2)
{
ICLASS:      VREDUCEPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR UIMM8()
OPERANDS:    REG0=YMM_R3():w:qq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b
IFORM:       VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_VL256RC
}


# EMITTING VRNDSCALEPD (VRNDSCALEPD-256-2)
{
ICLASS:      VRNDSCALEPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() SAE256() NOEVSR UIMM8()
OPERANDS:    REG0=YMM_R3():w:qq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b
IFORM:       VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_VL256RC
}


# EMITTING VRNDSCALEPH (VRNDSCALEPH-256-2)
{
ICLASS:      VRNDSCALEPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR UIMM8()
OPERANDS:    REG0=YMM_R3():w:qq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 IMM0:r:b
IFORM:       VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_VL256RC
}


# EMITTING VRNDSCALEPS (VRNDSCALEPS-256-2)
{
ICLASS:      VRNDSCALEPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR UIMM8()
OPERANDS:    REG0=YMM_R3():w:qq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b
IFORM:       VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_VL256RC
}


# EMITTING VSCALEFPD (VSCALEFPD-256-2)
{
ICLASS:      VSCALEFPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():w:qq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
IFORM:       VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC
}


# EMITTING VSCALEFPH (VSCALEFPH-256-2)
{
ICLASS:      VSCALEFPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():w:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC
}


# EMITTING VSCALEFPS (VSCALEFPS-256-2)
{
ICLASS:      VSCALEFPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC
}


# EMITTING VSQRTPD (VSQRTPD-256-2)
{
ICLASS:      VSQRTPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
IFORM:       VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512_VL256RC
}


# EMITTING VSQRTPH (VSQRTPH-256-2)
{
ICLASS:      VSQRTPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512_VL256RC
}


# EMITTING VSQRTPS (VSQRTPS-256-2)
{
ICLASS:      VSQRTPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512_VL256RC
}


# EMITTING VSUBPD (VSUBPD-256-2)
{
ICLASS:      VSUBPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():w:qq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
IFORM:       VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC
}


# EMITTING VSUBPH (VSUBPH-256-2)
{
ICLASS:      VSUBPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():w:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC
}


# EMITTING VSUBPS (VSUBPS-256-2)
{
ICLASS:      VSUBPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC
}


