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EVEX_INSTRUCTIONS()::
# EMITTING VMINMAXBF16 (VMINMAXBF16-128-1)
{
ICLASS:      VMINMAXBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x52 VF2 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 UIMM8()
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 REG3=XMM_B3():r:dq:bf16 IMM0:r:b
IFORM:       VMINMAXBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_IMM8_AVX512
}

{
ICLASS:      VMINMAXBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x52 VF2 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 UIMM8() ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
IFORM:       VMINMAXBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_IMM8_AVX512
}


# EMITTING VMINMAXBF16 (VMINMAXBF16-256-1)
{
ICLASS:      VMINMAXBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x52 VF2 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 UIMM8()
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 REG3=YMM_B3():r:qq:bf16 IMM0:r:b
IFORM:       VMINMAXBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_IMM8_AVX512
}

{
ICLASS:      VMINMAXBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x52 VF2 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 UIMM8() ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
IFORM:       VMINMAXBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_IMM8_AVX512
}


# EMITTING VMINMAXBF16 (VMINMAXBF16-512-1)
{
ICLASS:      VMINMAXBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x52 VF2 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 UIMM8()
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 REG3=ZMM_B3():r:zbf16 IMM0:r:b
IFORM:       VMINMAXBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_IMM8_AVX512
}

{
ICLASS:      VMINMAXBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x52 VF2 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 UIMM8() ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
IFORM:       VMINMAXBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_IMM8_AVX512
}


# EMITTING VMINMAXPD (VMINMAXPD-128-1)
{
ICLASS:      VMINMAXPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x52 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W1 VL128 UIMM8()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
IFORM:       VMINMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
}

{
ICLASS:      VMINMAXPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x52 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W1 VL128 UIMM8() ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
IFORM:       VMINMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
}


# EMITTING VMINMAXPD (VMINMAXPD-256-1)
{
ICLASS:      VMINMAXPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x52 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W1 VL256 UIMM8()
OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b
IFORM:       VMINMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512
}

{
ICLASS:      VMINMAXPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x52 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() SAE256() UIMM8()
OPERANDS:    REG0=YMM_R3():w:qq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b
IFORM:       VMINMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512
}

{
ICLASS:      VMINMAXPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x52 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W1 VL256 UIMM8() ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
IFORM:       VMINMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512
}


# EMITTING VMINMAXPD (VMINMAXPD-512-1)
{
ICLASS:      VMINMAXPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x52 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W1 VL512 UIMM8()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b
IFORM:       VMINMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
}

{
ICLASS:      VMINMAXPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x52 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN512() SAE() UIMM8()
OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b
IFORM:       VMINMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
}

{
ICLASS:      VMINMAXPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x52 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W1 VL512 UIMM8() ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
IFORM:       VMINMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512
}


# EMITTING VMINMAXPH (VMINMAXPH-128-1)
{
ICLASS:      VMINMAXPH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x52 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 UIMM8()
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
IFORM:       VMINMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
}

{
ICLASS:      VMINMAXPH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:     EVV 0x52 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 UIMM8() ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
IFORM:       VMINMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512
}


# EMITTING VMINMAXPH (VMINMAXPH-256-1)
{
ICLASS:      VMINMAXPH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x52 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 UIMM8()
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 IMM0:r:b
IFORM:       VMINMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_IMM8_AVX512
}

{
ICLASS:      VMINMAXPH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x52 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() UIMM8()
OPERANDS:    REG0=YMM_R3():w:qq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 IMM0:r:b
IFORM:       VMINMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_IMM8_AVX512
}

{
ICLASS:      VMINMAXPH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:     EVV 0x52 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 UIMM8() ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
IFORM:       VMINMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_IMM8_AVX512
}


# EMITTING VMINMAXPH (VMINMAXPH-512-1)
{
ICLASS:      VMINMAXPH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x52 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 UIMM8()
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 IMM0:r:b
IFORM:       VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512
}

{
ICLASS:      VMINMAXPH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x52 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN512() SAE() UIMM8()
OPERANDS:    REG0=ZMM_R3():w:zf16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 IMM0:r:b
IFORM:       VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512
}

{
ICLASS:      VMINMAXPH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:     EVV 0x52 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 UIMM8() ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
IFORM:       VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512
}


# EMITTING VMINMAXPS (VMINMAXPS-128-1)
{
ICLASS:      VMINMAXPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x52 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 UIMM8()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
IFORM:       VMINMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
}

{
ICLASS:      VMINMAXPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x52 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 UIMM8() ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
IFORM:       VMINMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
}


# EMITTING VMINMAXPS (VMINMAXPS-256-1)
{
ICLASS:      VMINMAXPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x52 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 UIMM8()
OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b
IFORM:       VMINMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512
}

{
ICLASS:      VMINMAXPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x52 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() UIMM8()
OPERANDS:    REG0=YMM_R3():w:qq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b
IFORM:       VMINMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512
}

{
ICLASS:      VMINMAXPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x52 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 UIMM8() ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
IFORM:       VMINMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512
}


# EMITTING VMINMAXPS (VMINMAXPS-512-1)
{
ICLASS:      VMINMAXPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x52 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 UIMM8()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b
IFORM:       VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
}

{
ICLASS:      VMINMAXPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x52 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN512() SAE() UIMM8()
OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b
IFORM:       VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
}

{
ICLASS:      VMINMAXPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x52 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 UIMM8() ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
IFORM:       VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
}


# EMITTING VMINMAXSD (VMINMAXSD-128-1)
{
ICLASS:      VMINMAXSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x53 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() UIMM8()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
IFORM:       VMINMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
}

{
ICLASS:      VMINMAXSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x53 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() SAE() UIMM8()
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
IFORM:       VMINMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
}

{
ICLASS:      VMINMAXSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x53 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W1 FIX_ROUND_LEN128() UIMM8() ESIZE_64_BITS() NELEM_ONE()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b
IFORM:       VMINMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
}


# EMITTING VMINMAXSH (VMINMAXSH-128-1)
{
ICLASS:      VMINMAXSH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x53 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() UIMM8()
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
IFORM:       VMINMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
}

{
ICLASS:      VMINMAXSH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x53 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE() UIMM8()
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
IFORM:       VMINMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
}

{
ICLASS:      VMINMAXSH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x53 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 FIX_ROUND_LEN128() UIMM8() ESIZE_16_BITS() NELEM_ONE()
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 IMM0:r:b
IFORM:       VMINMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512
}


# EMITTING VMINMAXSS (VMINMAXSS-128-1)
{
ICLASS:      VMINMAXSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x53 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() UIMM8()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
IFORM:       VMINMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
}

{
ICLASS:      VMINMAXSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x53 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE() UIMM8()
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
IFORM:       VMINMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
}

{
ICLASS:      VMINMAXSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MINMAX_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x53 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 FIX_ROUND_LEN128() UIMM8() ESIZE_32_BITS() NELEM_ONE()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b
IFORM:       VMINMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
}


